1. Field of the Invention
The invention relates to a transistor varactor structure for a dynamic semiconductor storage means formed on a doped silicon substrate.
2. Description of the Prior Art
A basic structure for dynamic conductor storage means, referred to as DRAMs, consists of a transistor varactor cell. The transistor is designed as a MOS-FET and can be externally controlled by way of externally contacted source and drain regions. The drain region is electrically connected to one electrode side of the varactor and the second electrode side is externally controlled by a contact terminal. In the case of transistor varactors with packing densities of one megabit per square centimeter, the varactors are generally of a planar form and the varactor consists of a doped layer of silicon substrate and a planar polysilicon layer separated by a dielectric layer. In order to increase the packing density of the dynamic storage means (DRAMs) due to the smaller cell surface areas available and due to capacitive values of 30-50 pF which are required for resistance to interference, new varactor design concepts are needed. One possibility of meeting these demands, in other words, reduced space requirements and minimum capacitance of the varactor, consists in constructing the varactor as a stacked capacitor. The stacked capacitor consists of two polysilicon layers with a separating dielectric layer which are not formed as planar layers, but overlap the gate electrode of the field effect transistor.
It is known that a stacked capacitor can be used to increase the degree of integration of dynamic semiconductor stores as, for example, as described in the article IEEE Transaction on Electron Devices Volume ED-27 No. 8, August 1980 entitled "A 5 V only 16 kbit Stacked-Capacitor MOS Ram" by Mitsumasa Koyanagi, Yoshio Sakai, Masamichi Ishihara, Masanori Tazunoki and Norikazu Hashimoto, pages 1596 to 1601. As described in this publication, a stacked capacitor is constructed from a two layer polysilicon formation with a silicon nitride layer Si.sub.3 N.sub.4 (generally Poly Si-Si.sub.3 N.sub.4 -Poly Si or Al). FIG. 1 of this publication shows three stacked capacitor cell structures (A) "top capacitor" (B) "intermediate capacitor" and (C) "bottom capacitor". In embodiments A and B, the gate electrodes are partially overlapped by the stacked capacitors. In embodiment A the three-layer structure is a Poly Si-Si.sub.3 N.sub.4 -Al-layer, whereas an embodiment B it is a Poly Si-Si.sub.3 N.sub.4 -Poly Si-layer. In embodiment C, the "bottom capacitor"--the gate electrode partially covers the stacked capacitor which consists of a Poly Si-Si.sub.3 N.sub.4 -Poly Si-structure.
In the past, various other cell structures have been described which increase the degree of integration such as, for example, the CCB-cell (capacitance-coupled bit line cell). Such CCB-cell is discussed in the publication of the IEEE Journal of Solid State Circuits, Volume SC-20, No. 1, "A Capacitance-Coupled Bit Line Cell" by Masao Taguchi, Satoshi Ando, Shimpei Hijiya, Tetsuo Nakamura, Seiji Enomoto and Takashi Yabu, at pages 210 through 215. The principle of this cell consists of a capacitively coupled terminal of the source or drain regions. FIG. 1 of this publication gives a detailed explanation of the composition of the structure which consists of a three layer polysilicon arrangement. The first layer forms the gate electrode and the second and third layers form the varactor with a separating dielectric layer.
Another possibility of increasing the degree of integration is disclosed in the article "IEEE Electron Device Letters", Volume EDL-5, No. 5, May 1984, "A Three-Dimensional Folded Dynamic RAM in Beam-Recrystallized Polysilicon" by J. C. Sturm, M. D. Giles and J. F. Gibbons at pages 151 to 153. In this article, the transistor varactor arrangement is compressed wherein the first polysilicon layer of the varactor surrounds the other in a U-formation and the transistor is arranged above the second polysilicon layer of the varactor as illustrated in FIGS. 1 and 2. This arrangement is referred to as a dynamic folded RAM cell.
Other possibilities exist in the use of the "Hi-C" RAM-Cell (high capacity RAM Cell) described in SZE, VLSI Technology, at pages 476-478 published by McGraw-Hill, New York (1983). In this article, an arsenic implantation and a deeper extending boron implantation are done under the varactor so as to maximize the capacitance of the varactor by reduced cell surface areas. The implantation steps result in an additional blocking layer capacitance which increases the charge capacitance of the varactor. So as to produce a stacked capacitor and a transistor varactor cell, it has been previously necessary to utilize specific design spacings between the various layers due to adjustment tolerances of the individual layers relative to each other and so as to maintain the dimensional accuracy of the structural arrangement. If the spacings are not maintained, there is danger that a short circuit will occur between the layers. In a CCB cell concept due to the capacitive coupling of the source or drain zone, there is a danger of increasing the voltage between the terminals of the transistor at the instant when changes occur in the potential of the capacitive terminal contact. This is particularly critical in the case of transistor channel lengths of 0.7 to 1 .mu.m.